Experience

Dec 2018 – present Assistant Professor Department of Electronics and Communication Engineering, Manipur Technical University, Imphal
Jul 2014 – Oct 2016 ASIC Engineer NVIDIA Graphics Pvt. Ltd., Bangalore
Designed test logic for 14 nm and 10 nm SRAMs used in GPUs, and implemented and verified it at unit level: RTL synthesis, scan-chain insertion, ATPG pattern generation on the scan netlist and simulation of the patterns on RTL. Analyzed test coverage to find and close coverage holes. Performed X-analysis for Tegra SoCs for self-driving cars to meet the ISO 26262 automotive-safety standard for in-system testing.
May 2011 – Jun 2012 Design Engineer Sankalp Semiconductor Pvt. Ltd., Bangalore
Developed fully orthogonal macro-models of op-amps, with test benches and verification. Carried out bench characterization and testing of precision SAR ADCs, including full-chip post-silicon characterization on the bench and on automatic test equipment (ATE).

Education

2020 Ph.D. in VLSI Design National Institute of Technology Silchar
Thesis: Approximate Computing Based VLSI Design for Energy-Efficient Cascade Support Vector Machine
Supervisor: Dr. Madhuchhanda Choudhury, Associate Professor, NIT Silchar
2014 M.E. in Microelectronics Birla Institute of Technology and Science (BITS) Pilani, Pilani Campus
2011 B.E. in Electronics and Communication Engineering Manipal Institute of Technology, Manipal

ASIC designSynopsys: Design Compiler, PrimeTime, VCS, Verdi, TetraMAX · Cadence: Virtuoso, IUS, NCSim, RTL Compiler, SoC Encounter, Assura · Mentor Graphics HDL Designer
FPGA developmentAMD Vivado Design Suite
Simulation & analysisQuestaSim, HSPICE, PSPICE, MATLAB, LabVIEW, Eagle
LanguagesVerilog, VHDL, Python, Perl, Tcl, C, C++, Linux shell scripting
Hardware systemsSystem design with FPGAs, Arduino and Raspberry Pi